/*
 * ddr.h
 *
 * (C) Copyright 2012
 * Emcraft Systems, <www.emcraft.com>
 * Yuri Tikhonov, <yur@emcraft.com>
 *
 * Based on Microsemi firmware/CMSIS/sys_init_cfg_types.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef _DDR_H_
#define _DDR_H_

/*
 * MODE_CR bits
 */
#define REG_DDRC_MOBILE			7
#define REG_DDRC_SDRAM			6
#define REG_DDRC_DATA_BUS_WIDTH		0

/*
 * DYN_REFRESH_1_CR bits
 */
#define REG_DDRC_T_RFC_MIN		7
#define REG_DDRC_SELFREF_EN		5
#define REG_DDRC_REFRESH_TO_X32		0

/*
 * DYN_REFRESH_2_CR bits
 */
#define REG_DDRC_T_RFC_NOM_X32		3
#define REG_DDRC_REFRESH_BURST		0


/*
 * DYN_POWERDOWN_CR bits
 */
#define REG_DDRC_POWERDOWN_EN		1

/*
 * CKE_RSTN_CYCLES_1_CR bits
 */
#define REG_DDRC_PRE_CKE_X1024		8

/*
 * REG_DDRC_POST_CKE_X1024 bits
 */
#define REG_DDRC_POST_CKE_X1024		3

/*
 * DRAM_BANK_ACT_TIMING_CR bits
 */
#define REG_DDRC_T_RCD			10
#define REG_DDRC_T_CCD			7
#define REG_DDRC_T_RRD			4
#define REG_DDRC_T_RP			0

/*
 * DRAM_BANK_TIMING_PARAM_CR bits
 */
#define REG_DDRC_T_RC			6

/*
 * DRAM_RD_WR_LATENCY_CR bits
 */
#define REG_DDRC_WRITE_LATENCY		5
#define REG_DDRC_READ_LATENCY		0

/*
 * DRAM_MR_TIMING_PARAM_CR bits
 */
#define REG_DDRC_T_MRD			0

/*
 * DRAM_RAS_TIMING_CR bits
 */
#define REG_DDRC_T_RAS_MAX		5
#define REG_DDRC_T_RAS_MIN		0

/*
 * DRAM_RD_WR_TRNARND_TIME_CR bits
 */
#define REG_DDRC_RD2WR			5
#define REG_DDRC_WR2RD			0

/*
 * DFI_RDDATA_EN_CR bits
 */
#define REG_DDRC_DFI_T_RDDATA_EN	0

/*
 * DRAM_RD_WR_PRE_CR bits
 */
#define REG_DDRC_WR2PRE			5
#define REG_DDRC_RD2PRE			0

/*
 * DRAM_T_PD_CR bits
 */
#define REG_DDRC_T_XP			4
#define REG_DDRC_T_CKE			0

/*
 * PERF_PARAM_1_CR bits
 */
#define REG_DDRC_BURST_RDWR		13
#define REG_DDRC_PAGECLOSE		0x10

/*
 * PERF_PARAM_2_CR bits
 */
#define REG_DDRC_BURST_MODE		10

/*
 * DDRC_PWR_SAVE_1_CR bits
 */
#define REG_DDRC_POWERDOWN_TO_X32_SHIFT		1
#define REG_DDRC_POST_SELFREF_GAP_X32_SHIFT	6

/*
 * DDR Configuration registers
 */
struct ddr_regs {
	/*
	 * DDR Controller registers.
	 */
	struct {
		u32	DYN_SOFT_RESET_CR;
		u32	RESERVED0;
		u32	DYN_REFRESH_1_CR;
		u32	DYN_REFRESH_2_CR;
		u32	DYN_POWERDOWN_CR;
		u32	DYN_DEBUG_CR;
		u32	MODE_CR;
		u32	ADDR_MAP_BANK_CR;
		u32	ECC_DATA_MASK_CR;
		u32	ADDR_MAP_COL_1_CR;
		u32	ADDR_MAP_COL_2_CR;
		u32	ADDR_MAP_ROW_1_CR;
		u32	ADDR_MAP_ROW_2_CR;
		u32	INIT_1_CR;
		u32	CKE_RSTN_CYCLES_1_CR;
		u32	CKE_RSTN_CYCLES_2_CR;
		u32	INIT_MR_CR;
		u32	INIT_EMR_CR;
		u32	INIT_EMR2_CR;
		u32	INIT_EMR3_CR;
		u32	DRAM_BANK_TIMING_PARAM_CR;
		u32	DRAM_RD_WR_LATENCY_CR;
		u32	DRAM_RD_WR_PRE_CR;
		u32	DRAM_MR_TIMING_PARAM_CR;
		u32	DRAM_RAS_TIMING_CR;
		u32	DRAM_RD_WR_TRNARND_TIME_CR;
		u32	DRAM_T_PD_CR;
		u32	DRAM_BANK_ACT_TIMING_CR;
		u32	ODT_PARAM_1_CR;
		u32	ODT_PARAM_2_CR;
		u32	ADDR_MAP_COL_3_CR;
		u32	MODE_REG_RD_WR_CR;
		u32	MODE_REG_DATA_CR;
		u32	PWR_SAVE_1_CR;
		u32	PWR_SAVE_2_CR;
		u32	ZQ_LONG_TIME_CR;
		u32	ZQ_SHORT_TIME_CR;
		u32	ZQ_SHORT_INT_REFRESH_MARGIN_1_CR;
		u32	ZQ_SHORT_INT_REFRESH_MARGIN_2_CR;
		u32	PERF_PARAM_1_CR;
		u32	HPR_QUEUE_PARAM_1_CR;
		u32	HPR_QUEUE_PARAM_2_CR;
		u32	LPR_QUEUE_PARAM_1_CR;
		u32	LPR_QUEUE_PARAM_2_CR;
		u32	WR_QUEUE_PARAM_CR;
		u32	PERF_PARAM_2_CR;
		u32	PERF_PARAM_3_CR;
		u32	DFI_RDDATA_EN_CR;
		u32	DFI_MIN_CTRLUPD_TIMING_CR;
		u32	DFI_MAX_CTRLUPD_TIMING_CR;
		u32	DFI_WR_LVL_CONTROL_1_CR;
		u32	DFI_WR_LVL_CONTROL_2_CR;
		u32	DFI_RD_LVL_CONTROL_1_CR;
		u32	DFI_RD_LVL_CONTROL_2_CR;
		u32	DFI_CTRLUPD_TIME_INTERVAL_CR;
		u32	DYN_SOFT_RESET_CR2;
		u32	AXI_FABRIC_PRI_ID_CR;
		u32	SR;
		u32	SINGLE_ERR_CNT_STATUS_SR;
		u32	DOUBLE_ERR_CNT_STATUS_SR;
		u32	LUE_SYNDROME_1_SR;
		u32	LUE_SYNDROME_2_SR;
		u32	LUE_SYNDROME_3_SR;
		u32	LUE_SYNDROME_4_SR;
		u32	LUE_SYNDROME_5_SR;
		u32	LUE_ADDRESS_1_SR;
		u32	LUE_ADDRESS_2_SR;
		u32	LCE_SYNDROME_1_SR;
		u32	LCE_SYNDROME_2_SR;
		u32	LCE_SYNDROME_3_SR;
		u32	LCE_SYNDROME_4_SR;
		u32	LCE_SYNDROME_5_SR;
		u32	LCE_ADDRESS_1_SR;
		u32	LCE_ADDRESS_2_SR;
		u32	LCB_NUMBER_SR;
		u32	LCB_MASK_1_SR;
		u32	LCB_MASK_2_SR;
		u32	LCB_MASK_3_SR;
		u32	LCB_MASK_4_SR;
		u32	ECC_INT_SR;
		u32	ECC_INT_CLR_REG;
	} ddrc;

	u32	reserved0[(0x200 - 0x144) >> 2];

	/*
	 * DDR PHY configuration registers
	 */
	struct {
		u32	DYN_BIST_TEST_CR;
		u32	DYN_BIST_TEST_ERRCLR_1_CR;
		u32	DYN_BIST_TEST_ERRCLR_2_CR;
		u32	DYN_BIST_TEST_ERRCLR_3_CR;
		u32	BIST_TEST_SHIFT_PATTERN_1_CR;
		u32	BIST_TEST_SHIFT_PATTERN_2_CR;
		u32	BIST_TEST_SHIFT_PATTERN_3_CR;
		u32	DYN_LOOPBACK_TEST_CR;
		u32	BOARD_LOOPBACK_CR;
		u32	CTRL_SLAVE_RATIO_CR;
		u32	CTRL_SLAVE_FORCE_CR;
		u32	CTRL_SLAVE_DELAY_CR;
		u32	DATA_SLICE_IN_USE_CR;
		u32	LVL_NUM_OF_DQ0_CR;
		u32	DQ_OFFSET_1_CR;
		u32	DQ_OFFSET_2_CR;
		u32	DQ_OFFSET_3_CR;
		u32	DIS_CALIB_RST_CR;
		u32	DLL_LOCK_DIFF_CR;
		u32	FIFO_WE_IN_DELAY_1_CR;
		u32	FIFO_WE_IN_DELAY_2_CR;
		u32	FIFO_WE_IN_DELAY_3_CR;
		u32	FIFO_WE_IN_FORCE_CR;
		u32	FIFO_WE_SLAVE_RATIO_1_CR;
		u32	FIFO_WE_SLAVE_RATIO_2_CR;
		u32	FIFO_WE_SLAVE_RATIO_3_CR;
		u32	FIFO_WE_SLAVE_RATIO_4_CR;
		u32	GATELVL_INIT_MODE_CR;
		u32	GATELVL_INIT_RATIO_1_CR;
		u32	GATELVL_INIT_RATIO_2_CR;
		u32	GATELVL_INIT_RATIO_3_CR;
		u32	GATELVL_INIT_RATIO_4_CR;
		u32	LOCAL_ODT_CR;
		u32	INVERT_CLKOUT_CR;
		u32	RD_DQS_SLAVE_DELAY_1_CR;
		u32	RD_DQS_SLAVE_DELAY_2_CR;
		u32	RD_DQS_SLAVE_DELAY_3_CR;
		u32	RD_DQS_SLAVE_FORCE_CR;
		u32	RD_DQS_SLAVE_RATIO_1_CR;
		u32	RD_DQS_SLAVE_RATIO_2_CR;
		u32	RD_DQS_SLAVE_RATIO_3_CR;
		u32	RD_DQS_SLAVE_RATIO_4_CR;
		u32	WR_DQS_SLAVE_DELAY_1_CR;
		u32	WR_DQS_SLAVE_DELAY_2_CR;
		u32	WR_DQS_SLAVE_DELAY_3_CR;
		u32	WR_DQS_SLAVE_FORCE_CR;
		u32	WR_DQS_SLAVE_RATIO_1_CR;
		u32	WR_DQS_SLAVE_RATIO_2_CR;
		u32	WR_DQS_SLAVE_RATIO_3_CR;
		u32	WR_DQS_SLAVE_RATIO_4_CR;
		u32	WR_DATA_SLAVE_DELAY_1_CR;
		u32	WR_DATA_SLAVE_DELAY_2_CR;
		u32	WR_DATA_SLAVE_DELAY_3_CR;
		u32	WR_DATA_SLAVE_FORCE_CR;
		u32	WR_DATA_SLAVE_RATIO_1_CR;
		u32	WR_DATA_SLAVE_RATIO_2_CR;
		u32	WR_DATA_SLAVE_RATIO_3_CR;
		u32	WR_DATA_SLAVE_RATIO_4_CR;
		u32	WRLVL_INIT_MODE_CR;
		u32	WRLVL_INIT_RATIO_1_CR;
		u32	WRLVL_INIT_RATIO_2_CR;
		u32	WRLVL_INIT_RATIO_3_CR;
		u32	WRLVL_INIT_RATIO_4_CR;
		u32	WR_RD_RL_CR;
		u32	RDC_FIFO_RST_ERRCNTCLR_CR;
		u32	RDC_WE_TO_RE_DELAY_CR;
		u32	USE_FIXED_RE_CR;
		u32	USE_RANK0_DELAYS_CR;
		u32	USE_LVL_TRNG_LEVEL_CR;
		u32	DYN_CONFIG_CR;
		u32	RD_WR_GATE_LVL_CR;
		u32	DYN_RESET_CR;
		u32	LEVELLING_FAILURE_SR;
		u32	BIST_ERROR_1_SR;
		u32	BIST_ERROR_2_SR;
		u32	BIST_ERROR_3_SR;
		u32	WRLVL_DQS_RATIO_1_SR;
		u32	WRLVL_DQS_RATIO_2_SR;
		u32	WRLVL_DQS_RATIO_3_SR;
		u32	WRLVL_DQS_RATIO_4_SR;
		u32	WRLVL_DQ_RATIO_1_SR;
		u32	WRLVL_DQ_RATIO_2_SR;
		u32	WRLVL_DQ_RATIO_3_SR;
		u32	WRLVL_DQ_RATIO_4_SR;
		u32	RDLVL_DQS_RATIO_1_SR;
		u32	RDLVL_DQS_RATIO_2_SR;
		u32	RDLVL_DQS_RATIO_3_SR;
		u32	RDLVL_DQS_RATIO_4_SR;
		u32	FIFO_1_SR;
		u32	FIFO_2_SR;
		u32	FIFO_3_SR;
		u32	FIFO_4_SR;
		u32	MASTER_DLL_SR;
		u32	DLL_SLAVE_VALUE_1_SR;
		u32	DLL_SLAVE_VALUE_2_SR;
		u32	STATUS_OF_IN_DELAY_VAL_1_SR;
		u32	STATUS_OF_IN_DELAY_VAL_2_SR;
		u32	STATUS_OF_OUT_DELAY_VAL_1_SR;
		u32	STATUS_OF_OUT_DELAY_VAL_2_SR;
		u32	DLL_LOCK_AND_SLAVE_VAL_SR;
		u32	CTRL_OUTPUT_FILTER_SR;
		u32	RESERVED0;
		u32	RD_DQS_SLAVE_DLL_VAL_1_SR;
		u32	RD_DQS_SLAVE_DLL_VAL_2_SR;
		u32	RD_DQS_SLAVE_DLL_VAL_3_SR;
		u32	WR_DATA_SLAVE_DLL_VAL_1_SR;
		u32	WR_DATA_SLAVE_DLL_VAL_2_SR;
		u32	WR_DATA_SLAVE_DLL_VAL_3_SR;
		u32	FIFO_WE_SLAVE_DLL_VAL_1_SR;
		u32	FIFO_WE_SLAVE_DLL_VAL_2_SR;
		u32	FIFO_WE_SLAVE_DLL_VAL_3_SR;
		u32	WR_DQS_SLAVE_DLL_VAL_1_SR;
		u32	WR_DQS_SLAVE_DLL_VAL_2_SR;
		u32	WR_DQS_SLAVE_DLL_VAL_3_SR;
		u32	CTRL_SLAVE_DLL_VAL_SR;
	} phy;

	u32	reserved1[(0x400 - 0x3CC) >> 2];

	/*
	 * FIC-64 registers
	 */
	struct  {
		u32	NB_ADDR_CR;
		u32	NBRWB_SIZE_CR;
		u32	WB_TIMEOUT_CR;
		u32	HPD_SW_RW_EN_CR;
		u32	HPD_SW_RW_INVAL_CR;
		u32	SW_WR_ERCLR_CR;
		u32	ERR_INT_ENABLE_CR;
		u32	NUM_AHB_MASTERS_CR;
		u32	LOCK_TIMEOUTVAL_1_CR;
		u32	LOCK_TIMEOUTVAL_2_CR;
		u32	LOCK_TIMEOUT_EN_CR;
	} fic;
};

#endif /* _DDR_H_ */
